1. Technical Field
The present invention relates to semiconductor technology and more particularly to devices and methods for fabrication of a stressed device channel.
2. Description of the Related Art
Thin channel metal oxide semiconductor field effect transistor (MOSFET) structures such as ultrathin body semiconductor-on-insulator (SOI), FinFET, trigate, and nanowires, are considered viable options for device scaling in 22 nm node and beyond. However, most of the stress elements used in bulk technology cannot be used for thin channel devices. For example, embedded stressors such as SiGe and Si:C may not be employed for thin device channels.
One of the methods used to boost the transistor performance is the “stress memorization technique”. Two mechanisms are known for this technique: (1) stress memorization in a gate electrode, and (2) stress memorization in source/drain (S/D) regions. With the advent of metal-high-k gate stacks, these approaches are not viable. Approach (1) is very difficult to implement with metal-high-k gate stacks, and approach (2) cannot be used with thin channel structures because once amorphized, the S/D region cannot be recrystallized.